The present invention relates in general to semiconductor devices and their fabrication. More specifically, the present invention relates to a co-integrated fabrication process for forming vertically stacked and isolated n-type and p-type nanosheet/nanowire transistors on the same substrate.
In contemporary semiconductor device fabrication processes, a large number of semiconductor devices, such as silicon channel n-type field effect transistors (nFETs) and silicon germanium channel p-type field effect transistors (pFETs), are fabricated on a single wafer. Non-planar transistor device architectures, such as nanosheet (or nanowire) transistors, can provide increased device density and increased performance over planar transistors. Nanosheet transistors, in contrast to conventional planar FETs, include a gate stack that wraps around the full perimeter of multiple nanosheet channel regions. Nanosheet transistor configurations enable fuller depletion in the nanosheet channel regions and reduce short-channel effects.